delta-sigma ADC in FPGA

[Rick C]

Usually when I ask about delta-sigma ADCs in FPGAs the comments are along the lines of "terrible idea", "can't mix analog and digital", etc. I'm very much not convinced.

I think people have a view of the ADC as being a device with very balanced specs, resolution, SNR, etc. In this application we need significantly more resolution than we do accuracy. The measurement is differential pressure across an orifice in a gas flow rate sensor. The conversion curve for pressure to flow rate has a square root. This makes the measurement much more sensitive to resolution at the low end.

The signal is the human breath with a very low frequency content. The fundamental is 0.5 Hz maximum with various harmonic content. Our sample rate is 200 Hz.

The analog input circuit approximates the delta-sigma model with resistors from the input and the feedback summing currents to an integrating capacitor. The capacitor voltage is compared to a Vref (very accurately 1/2 Vcco) with a differential input on the FPGA. The Vcco for this I/O bank is isolated from other supplies and no other signals are on this power rail.

The processing of the captured signal is a simple counter, accumulate and dump. Many texts on this design show the use of a second stage of filtering which I believe is mostly present to shape the frequency response of the CIC filter. This is not useful in this application.

In a post elsewhere someone commented that a boxcar filter (the accumulate and dump) is not equivalent to a CIC filter, but without explaining. I can't see the distinction other than the CIC offers configurations that the boxcar filter doesn't. But certainly the boxcar filter gives identical results to a configuration of CIC filter.

[navaide]

Usually when I ask about delta-sigma ADCs in FPGAs the comments are along the lines of "terrible idea", "can't mix analog and digital", etc. I'm very much not convinced.
I think people have a view of the ADC as being a device with very balanced specs, resolution, SNR, etc. In this application we need significantly more resolution than we do accuracy. The measurement is differential pressure across an orifice in a gas flow rate sensor. The conversion curve for pressure to flow rate has a square root. This makes the measurement much more sensitive to resolution at the low end.
The signal is the human breath with a very low frequency content. The fundamental is 0.5 Hz maximum with various harmonic content. Our sample rate is 200 Hz.
The analog input circuit approximates the delta-sigma model with resistors from the input and the feedback summing currents to an integrating capacitor. The capacitor voltage is compared to a Vref (very accurately 1/2 Vcco) with a differential input on the FPGA. The Vcco for this I/O bank is isolated from other supplies and no other signals are on this power rail.
The processing of the captured signal is a simple counter, accumulate and dump. Many texts on this design show the use of a second stage of filtering which I believe is mostly present to shape the frequency response of the CIC filter. This is not useful in this application.
In a post elsewhere someone commented that a boxcar filter (the accumulate and dump) is not equivalent to a CIC filter, but without explaining. I can't see the distinction other than the CIC offers configurations that the boxcar filter doesn't. But certainly the boxcar filter gives identical results to a configuration of CIC filter.
--
Rick C.
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[Rick C]

I was drawing up the circuit in LTspice for someone to use as a guide to drawing the board level schematics. The input signals have a 0-5V range and are ratiometric to the sensor power rail, so the Vcco on the FPGA port pins for the ADC will need to be 3.3V, ratiometric to the 5V sensor rail. The input circuit for the ADC will require a voltage divider and the various resistors will need to have tight tolerances either in three values or multiple resistors can be combined using four of two values or six of a single value.

An alternative to this is to use a level shifter to provide a full 5V swing. The ratiometric 3.3V supply is no longer needed and the resistors simplify to two components of a single value. But it appears the ultimate limitation becomes the symmetry of the buffer switching. Imbalances in the rise/fall times or imbalances in the propagation delays will distort the impact on the integrated value on the capacitor. My clock period is 30 ns, which is not hugely larger than the timing properties of the buffers available in 5 volt logic.

I've found a very few parts that list symmetrical limits on the prop delays. I assume that means they will track better than other devices. It will be interesting to test these ADC.

[boB]

On Wed, 18 Nov 2020 15:07:32 -0800 (PST), Rick C

Post by Rick C
I was drawing up the circuit in LTspice for someone to use as a guide to drawing the board level schematics. The input signals have a 0-5V range and are ratiometric to the sensor power rail, so the Vcco on the FPGA port pins for the ADC will need to be 3.3V, ratiometric to the 5V sensor rail. The input circuit for the ADC will require a voltage divider and the various resistors will need to have tight tolerances either in three values or multiple resistors can be combined using four of two values or six of a single value.
An alternative to this is to use a level shifter to provide a full 5V swing. The ratiometric 3.3V supply is no longer needed and the resistors simplify to two components of a single value. But it appears the ultimate limitation becomes the symmetry of the buffer switching. Imbalances in the rise/fall times or imbalances in the propagation delays will distort the impact on the integrated value on the capacitor. My clock period is 30 ns, which is not hugely larger than the timing properties of the buffers available in 5 volt logic.
I've found a very few parts that list symmetrical limits on the prop delays. I assume that means they will track better than other devices. It will be interesting to test these ADC.

Will it work down to DC ya think ?

[Rick C]

Post by boB
On Wed, 18 Nov 2020 15:07:32 -0800 (PST), Rick C

I was drawing up the circuit in LTspice for someone to use as a guide to drawing the board level schematics. The input signals have a 0-5V range and are ratiometric to the sensor power rail, so the Vcco on the FPGA port pins for the ADC will need to be 3.3V, ratiometric to the 5V sensor rail. The input circuit for the ADC will require a voltage divider and the various resistors will need to have tight tolerances either in three values or multiple resistors can be combined using four of two values or six of a single value.
An alternative to this is to use a level shifter to provide a full 5V swing. The ratiometric 3.3V supply is no longer needed and the resistors simplify to two components of a single value. But it appears the ultimate limitation becomes the symmetry of the buffer switching. Imbalances in the rise/fall times or imbalances in the propagation delays will distort the impact on the integrated value on the capacitor. My clock period is 30 ns, which is not hugely larger than the timing properties of the buffers available in 5 volt logic.
I've found a very few parts that list symmetrical limits on the prop delays. I assume that means they will track better than other devices. It will be interesting to test these ADC.

Will it work down to DC ya think ?

That's what I'm counting on. The measurements we are making are pretty low bandwidth. One of the measurements is O2 level from a sensor that takes seconds to respond to a change in O2 levels, essentially DC. Why would you think it would not be sensitive to DC? We may measure the battery voltage this way as well.

[boB]

On Thu, 19 Nov 2020 11:44:04 -0800 (PST), Rick C

Post by Rick C

Post by boB
On Wed, 18 Nov 2020 15:07:32 -0800 (PST), Rick C

I was drawing up the circuit in LTspice for someone to use as a guide to drawing the board level schematics. The input signals have a 0-5V range and are ratiometric to the sensor power rail, so the Vcco on the FPGA port pins for the ADC will need to be 3.3V, ratiometric to the 5V sensor rail. The input circuit for the ADC will require a voltage divider and the various resistors will need to have tight tolerances either in three values or multiple resistors can be combined using four of two values or six of a single value.
An alternative to this is to use a level shifter to provide a full 5V swing. The ratiometric 3.3V supply is no longer needed and the resistors simplify to two components of a single value. But it appears the ultimate limitation becomes the symmetry of the buffer switching. Imbalances in the rise/fall times or imbalances in the propagation delays will distort the impact on the integrated value on the capacitor. My clock period is 30 ns, which is not hugely larger than the timing properties of the buffers available in 5 volt logic.
I've found a very few parts that list symmetrical limits on the prop delays. I assume that means they will track better than other devices. It will be interesting to test these ADC.

Will it work down to DC ya think ?

That's what I'm counting on. The measurements we are making are pretty low bandwidth. One of the measurements is O2 level from a sensor that takes seconds to respond to a change in O2 levels, essentially DC. Why would you think it would not be sensitive to DC? We may measure the battery voltage this way as well.

Most of the high sample rate, high bit width audio delta-sigmas don't
do DC too well or not at all. Not sure exactly why. The might be too
offset drifty ?

[Rick C]

Post by boB
On Thu, 19 Nov 2020 11:44:04 -0800 (PST), Rick C

Post by boB
On Wed, 18 Nov 2020 15:07:32 -0800 (PST), Rick C

I was drawing up the circuit in LTspice for someone to use as a guide to drawing the board level schematics. The input signals have a 0-5V range and are ratiometric to the sensor power rail, so the Vcco on the FPGA port pins for the ADC will need to be 3.3V, ratiometric to the 5V sensor rail. The input circuit for the ADC will require a voltage divider and the various resistors will need to have tight tolerances either in three values or multiple resistors can be combined using four of two values or six of a single value.
An alternative to this is to use a level shifter to provide a full 5V swing. The ratiometric 3.3V supply is no longer needed and the resistors simplify to two components of a single value. But it appears the ultimate limitation becomes the symmetry of the buffer switching. Imbalances in the rise/fall times or imbalances in the propagation delays will distort the impact on the integrated value on the capacitor. My clock period is 30 ns, which is not hugely larger than the timing properties of the buffers available in 5 volt logic.
I've found a very few parts that list symmetrical limits on the prop delays. I assume that means they will track better than other devices. It will be interesting to test these ADC.

Will it work down to DC ya think ?

That's what I'm counting on. The measurements we are making are pretty low bandwidth. One of the measurements is O2 level from a sensor that takes seconds to respond to a change in O2 levels, essentially DC. Why would you think it would not be sensitive to DC? We may measure the battery voltage this way as well.

Most of the high sample rate, high bit width audio delta-sigmas don't
do DC too well or not at all. Not sure exactly why. The might be too
offset drifty ?

I don't know much of how they are internally constructed. The circuit I'm using forms the sum of the input and feedback with two resistors tied to a capacitor. This signal is tied to the inverting input on a comparator and the positive input is connected to a mid-point voltage reference. With well matched resistors and adequately balanced drivers for the feedback signal, the resulting voltage on the cap will hover at Vref to within a very small amount making any given input produce a well defined bit density at the output of the modulator. I can't think of what might impact the DC drift in this setup. It is literally a closed control loop. I suppose you don't want to use a microphonic cap. Otherwise, what do you think limits these devices?

One reason why they might want to block DC is because it creates an offset that reduces the effective range of the AC input. These things are mostly used for audio signals, so they want to optimize that aspect. So they expect the device to be AC coupled and internally block any residual offset.

[boB]

On Fri, 20 Nov 2020 13:52:25 -0800 (PST), Rick C

Post by Rick C

Post by boB
On Thu, 19 Nov 2020 11:44:04 -0800 (PST), Rick C

Post by boB
On Wed, 18 Nov 2020 15:07:32 -0800 (PST), Rick C

I was drawing up the circuit in LTspice for someone to use as a guide to drawing the board level schematics. The input signals have a 0-5V range and are ratiometric to the sensor power rail, so the Vcco on the FPGA port pins for the ADC will need to be 3.3V, ratiometric to the 5V sensor rail. The input circuit for the ADC will require a voltage divider and the various resistors will need to have tight tolerances either in three values or multiple resistors can be combined using four of two values or six of a single value.
An alternative to this is to use a level shifter to provide a full 5V swing. The ratiometric 3.3V supply is no longer needed and the resistors simplify to two components of a single value. But it appears the ultimate limitation becomes the symmetry of the buffer switching. Imbalances in the rise/fall times or imbalances in the propagation delays will distort the impact on the integrated value on the capacitor. My clock period is 30 ns, which is not hugely larger than the timing properties of the buffers available in 5 volt logic.
I've found a very few parts that list symmetrical limits on the prop delays. I assume that means they will track better than other devices. It will be interesting to test these ADC.

Will it work down to DC ya think ?

That's what I'm counting on. The measurements we are making are pretty low bandwidth. One of the measurements is O2 level from a sensor that takes seconds to respond to a change in O2 levels, essentially DC. Why would you think it would not be sensitive to DC? We may measure the battery voltage this way as well.

Most of the high sample rate, high bit width audio delta-sigmas don't
do DC too well or not at all. Not sure exactly why. The might be too
offset drifty ?

I don't know much of how they are internally constructed. The circuit I'm using forms the sum of the input and feedback with two resistors tied to a capacitor. This signal is tied to the inverting input on a comparator and the positive input is connected to a mid-point voltage reference. With well matched resistors and adequately balanced drivers for the feedback signal, the resulting voltage on the cap will hover at Vref to within a very small amount making any given input produce a well defined bit density at the output of the modulator. I can't think of what might impact the DC drift in this setup. It is literally a closed control loop. I suppose you don't want to use a microphonic cap. Otherwise, what do you think limits these devices?
One reason why they might want to block DC is because it creates an offset that reduces the effective range of the AC input. These things are mostly used for audio signals, so they want to optimize that aspect. So they expect the device to be AC coupled and internally block any residual offset.

I think your last thought about not wanting to compromise the AC
range, rail to rail might be the reason. I seem to remember one of
the delta-signal audio converters had the option of disabling that HPF
though. Can't remember which one ? Crystal Semiconductor (Cypress
now ?) or AKM or Analog Devices ?

At least there are low-ish sample rate D-S converters now that have
high bit width and DC respinse though. Can't have everything I guess.

Are your input integrators /comparators internal to the FPGA ?

[Rick C]

Post by boB
On Fri, 20 Nov 2020 13:52:25 -0800 (PST), Rick C

Post by boB
On Thu, 19 Nov 2020 11:44:04 -0800 (PST), Rick C

Post by boB
On Wed, 18 Nov 2020 15:07:32 -0800 (PST), Rick C

I was drawing up the circuit in LTspice for someone to use as a guide to drawing the board level schematics. The input signals have a 0-5V range and are ratiometric to the sensor power rail, so the Vcco on the FPGA port pins for the ADC will need to be 3.3V, ratiometric to the 5V sensor rail. The input circuit for the ADC will require a voltage divider and the various resistors will need to have tight tolerances either in three values or multiple resistors can be combined using four of two values or six of a single value.
An alternative to this is to use a level shifter to provide a full 5V swing. The ratiometric 3.3V supply is no longer needed and the resistors simplify to two components of a single value. But it appears the ultimate limitation becomes the symmetry of the buffer switching. Imbalances in the rise/fall times or imbalances in the propagation delays will distort the impact on the integrated value on the capacitor. My clock period is 30 ns, which is not hugely larger than the timing properties of the buffers available in 5 volt logic.
I've found a very few parts that list symmetrical limits on the prop delays. I assume that means they will track better than other devices. It will be interesting to test these ADC.

Will it work down to DC ya think ?

That's what I'm counting on. The measurements we are making are pretty low bandwidth. One of the measurements is O2 level from a sensor that takes seconds to respond to a change in O2 levels, essentially DC. Why would you think it would not be sensitive to DC? We may measure the battery voltage this way as well.

Most of the high sample rate, high bit width audio delta-sigmas don't
do DC too well or not at all. Not sure exactly why. The might be too
offset drifty ?

I don't know much of how they are internally constructed. The circuit I'm using forms the sum of the input and feedback with two resistors tied to a capacitor. This signal is tied to the inverting input on a comparator and the positive input is connected to a mid-point voltage reference. With well matched resistors and adequately balanced drivers for the feedback signal, the resulting voltage on the cap will hover at Vref to within a very small amount making any given input produce a well defined bit density at the output of the modulator. I can't think of what might impact the DC drift in this setup. It is literally a closed control loop. I suppose you don't want to use a microphonic cap. Otherwise, what do you think limits these devices?
One reason why they might want to block DC is because it creates an offset that reduces the effective range of the AC input. These things are mostly used for audio signals, so they want to optimize that aspect. So they expect the device to be AC coupled and internally block any residual offset.

I think your last thought about not wanting to compromise the AC
range, rail to rail might be the reason. I seem to remember one of
the delta-signal audio converters had the option of disabling that HPF
though. Can't remember which one ? Crystal Semiconductor (Cypress
now ?) or AKM or Analog Devices ?

I use the AK4556 from AKM in a design and it allows the high pass filter to be disabled, not that I use that feature. The AK4556 is a pin superset of the AK4552 which does not have the ability to disable the high pass filter I believe.

Post by boB
At least there are low-ish sample rate D-S converters now that have
high bit width and DC respinse though. Can't have everything I guess.
Are your input integrators /comparators internal to the FPGA ?

LVDS receivers. The integrator is an RC as I've described. The inverting input of the comparator provides negative feedback to maintain the voltage on the cap equal to the Vref. The signal fundamental is 0.5 Hz with harmonics into the tens of Hz. With a 200 Hz sample rate we should have no trouble with bandwidth.

[boB]

On Fri, 20 Nov 2020 22:02:45 -0800 (PST), Rick C

Post by Rick C

Post by boB
On Fri, 20 Nov 2020 13:52:25 -0800 (PST), Rick C

Post by boB
On Thu, 19 Nov 2020 11:44:04 -0800 (PST), Rick C

Post by boB
On Wed, 18 Nov 2020 15:07:32 -0800 (PST), Rick C

I was drawing up the circuit in LTspice for someone to use as a guide to drawing the board level schematics. The input signals have a 0-5V range and are ratiometric to the sensor power rail, so the Vcco on the FPGA port pins for the ADC will need to be 3.3V, ratiometric to the 5V sensor rail. The input circuit for the ADC will require a voltage divider and the various resistors will need to have tight tolerances either in three values or multiple resistors can be combined using four of two values or six of a single value.
An alternative to this is to use a level shifter to provide a full 5V swing. The ratiometric 3.3V supply is no longer needed and the resistors simplify to two components of a single value. But it appears the ultimate limitation becomes the symmetry of the buffer switching. Imbalances in the rise/fall times or imbalances in the propagation delays will distort the impact on the integrated value on the capacitor. My clock period is 30 ns, which is not hugely larger than the timing properties of the buffers available in 5 volt logic.
I've found a very few parts that list symmetrical limits on the prop delays. I assume that means they will track better than other devices. It will be interesting to test these ADC.

Will it work down to DC ya think ?

That's what I'm counting on. The measurements we are making are pretty low bandwidth. One of the measurements is O2 level from a sensor that takes seconds to respond to a change in O2 levels, essentially DC. Why would you think it would not be sensitive to DC? We may measure the battery voltage this way as well.

Most of the high sample rate, high bit width audio delta-sigmas don't
do DC too well or not at all. Not sure exactly why. The might be too
offset drifty ?

I don't know much of how they are internally constructed. The circuit I'm using forms the sum of the input and feedback with two resistors tied to a capacitor. This signal is tied to the inverting input on a comparator and the positive input is connected to a mid-point voltage reference. With well matched resistors and adequately balanced drivers for the feedback signal, the resulting voltage on the cap will hover at Vref to within a very small amount making any given input produce a well defined bit density at the output of the modulator. I can't think of what might impact the DC drift in this setup. It is literally a closed control loop. I suppose you don't want to use a microphonic cap. Otherwise, what do you think limits these devices?
One reason why they might want to block DC is because it creates an offset that reduces the effective range of the AC input. These things are mostly used for audio signals, so they want to optimize that aspect. So they expect the device to be AC coupled and internally block any residual offset.

I think your last thought about not wanting to compromise the AC
range, rail to rail might be the reason. I seem to remember one of
the delta-signal audio converters had the option of disabling that HPF
though. Can't remember which one ? Crystal Semiconductor (Cypress
now ?) or AKM or Analog Devices ?

I use the AK4556 from AKM in a design and it allows the high pass filter to be disabled, not that I use that feature. The AK4556 is a pin superset of the AK4552 which does not have the ability to disable the high pass filter I believe.

I hope that the AKM factory gets back up and running next year after
their big fire recently

Post by Rick C

Post by boB
At least there are low-ish sample rate D-S converters now that have
high bit width and DC respinse though. Can't have everything I guess.
Are your input integrators /comparators internal to the FPGA ?

LVDS receivers. The integrator is an RC as I've described. The inverting input of the comparator provides negative feedback to maintain the voltage on the cap equal to the Vref. The signal fundamental is 0.5 Hz with harmonics into the tens of Hz. With a 200 Hz sample rate we should have no trouble with bandwidth.

The 16 bit 16 sample per second A/D I use for battery current sensing
(Microchip) does a zero offset null in-between each sample. Nice
feature to have.

[Rafael Deliano]

Fred Harris had a go at it once:
http://www.embeddedFORTH.de/temp/2000.pdf
But its a different application.

Vintage:
http://www.embeddedFORTH.de/temp/1973.pdf
No microprocessor then ( really took off >1974),
1 bit serial data looked attractive.
Note that CMOS analog switches came later too.

MfG JRD

[Rick C]

Post by Rafael Deliano
http://www.embeddedFORTH.de/temp/2000.pdf
But its a different application.
http://www.embeddedFORTH.de/temp/1973.pdf
No microprocessor then ( really took off >1974),
1 bit serial data looked attractive.
Note that CMOS analog switches came later too.
MfG JRD

Interesting, thanks.